HDL EDA Tools (Verilog, VHDL, SystemC, etc)



My personal preference is for Verilog at the moment, but I do hope to learn some SystemC as well. For whatever reasons, I am not a big fan of VHDL, so I'll likely tend to avoid that in my projects if I can.

Note: A number of these tools are available in the Fedora Electronics Lab and the Ubuntu Electronics Remix equivalent, which make it easier to get the set of tools installed and running.

HDL Language tools:

  • Verilog & SystemVerilog
    • Icarus Verilogis a free/open-source Verilog compiler and simulator for Linux.
    • Verilator is a free/open source Verilog compiler for Linux. As I understand, it compiles Verilog into SystemC/C++, and that result is run for simulation. Is said to run about 90 times faster than Icarus, which will be good for large things such as if I try to simulate Minimig. Here is a Tutorial on using Verilator to convert Verilog into a SystemC model.
    • vmodel uses Verilator to simulate Matlab verilog models. A lot of the docs etc. are in Russian though, so use your favorite online translator.
    • V2000 is a mixed-mode simulator for various inputs including Verilog.
    • Veriwell is a free/open source Verilog simulator, which used to be commercial.
    • gplcver is a free/open source Verilog simulator for Linux, which used to be commercial.
    • Vcomp is a free/open-source Verilog compiler that used to be commercial.
    • CvSDL is an open-source Verilog 2001/SystemC (co)simulator.
    • Veritak is an inexpensive shareware Verilog simulator, supporting most of Verilog 2001 and has a VHDL->Verilog translator. Here's a tutorial.
    • Vito converts behavioral Verilog into synthesizable one-hot code.
    • Jove is a Java based VPI kit comparable to Vera. Juno is an OpenVera to Jove translator.
    • APVM/Oroboro embeds Python into the Verilog simulation environment via VPI.
    • ScriptSim connects sims with Perl, Python and/or Tk scripts.
    • Verilog Design Checker sounds like a linting type tool, helping to see design problems.
    • V2Kparse seems to also be a linting type tool for Verilog.
    • Hana is a free/open-source Verilog analysis and synthesis tool.
    • vtagspython can give design heirarchy report and generate ctags-alike information for vim. I'd be more interested in the heirarchy report information.
    • Covered is a free/open-source Verilog code test coverage tool. This helps understand how well your simulation tests cover the design, to help improve test coverage and minimize errors that escape detection in simulation and other tests.
    • atpg is an open source library/API for adding atpg to your tools.
    • Odin II from Miami University is an open-source Verilog synthesis tool intended for academic research toward improving synthesis algorithms and methods.
    • Odin from University of Toronto is the precursor of Odin II
    • Open Verification Library (OVL) is an open library for assertions in Verilog, VHDL, SystemVerilog, and PSL-verilog. Sounds like they're considering adding support for PSL-vhdl and SystemC in the future. It seems that OVL may be usable with Icarus Verilog.
    • Universal Verification Methodology (UVM) is an open SystemVerioog library building upon OVM 2.1.1, VMM, and others. While based on OVM, it's intended to interoperate with VMM libraries as well. An Open-Source reference flow for UVM can be found here.
    • Open Verification Methodology (OVM) is an open SystemVerilog library for verification.
    • Verification Methodology Manual (VMM) is a System Verilog library for verification.
    • OpenVera is another Hardware Verification Language from Synopsys.
    • Teal/Truss from Trusster are open-source verification libraries in C++ and SystemVerilog.
    • RobustVerilog is some sort of Verilog preprocessor. I don't know what it does yet, I just now saw that a new project on OpenCores uses it.
    • CRC Tool is a free online tool to generate Verilog/VHDL CRC code.
    • PyHVL allows Verilog PLI usage of Python code for verification things.
    • Accelerra VIP is an interoperations library between VMM and OVM.
    • DoxVerilog is a Doxygen parser for generating documentation from Verilog/SystemVerilog sources.
    • Questa has various free tools for Verilog and VHDL.

  • VHDL
    • GHDL is a free-open-source compiler for VHDL design language. Hereis a note about the host gcc compiler version. Since GHDL seems to be a compiler from VHDL to something gcc operates on, if one could use GHDL and Verilator together for a mixed-language simulation ultimately done in SystemC/C++. Hmmm...
    • FreeHDL is another open-source VHDL simulator, and is part of the Quqs simulator project.
    • Clifton Labs hosts the current versions of Savant, TyVIS and Warped tools.
    • Alliance is a set of VHDL simulation, synthesis, and other chip EDA tools.
    • Vsyml is a symbolic simulator for VHDL.
    • CRC Tool is a free online tool to generate Verilog/VHDL CRC code.
    • Interconnection Network Generator is a Wishbone bus generator for multiprocessor systems, which outputs VHDL code.
    • vMagic is a Java API to read/process/write VHDL code.
    • Questa has various free tools for Verilog and VHDL.
    • Math2Mat converts Matlab/Octave code to VHDL, and claims that source will soon be available under GPL3 license.



    • ArchC is an Architecture Design Language based on SystemC.
    • ParC is an open-source Parallel C++ project aimed at extending C++ for use like an HDL language. It is developed as part of their open-source V2000 simulator project. Another project named ParC may or may not be related, this other one sounce like a software development tool.
    • SampaLib sounds like another C++ HDL environment.
    • ANVIL is a C++ testbench generator/simulator for Verilog DUT.

  • HDL Language translators
    • Sister is a free/open-source SystemC to Verilog translator
    • sc2v is a SystemC to Verilog translator for synthesizable SystemC RTL code.
    • Inferno is another SystemC to Verilog translator.
    • sysc2ver is another SystemC to Verilog translator.
    • osmosissynth is a SystemC synthesis tool with Verilog backend.
    • gscc is a set of SystemC tools including a translator to Verilog.
    • C to Verilog is an online translator from C code to Verilog code. Source code for their SystemRacer synthesis engine is available here under GPL3.
    • LegUp is a C to Verilog translator
    • c2verilog is also a C to verilog source translator.
    • NISC (No Instruction Set Computer) is a C to Verilog toolset.
    • ROCCC is a free/open source C to VHDL compiler.
    • LegUp is another C to Verilog translator.
    • sc2vhdl is a SystemC to VHDL translator.
    • Gaut is an Ansi-C to VHDL translator.
    • vhdl_lut_gen converts Lookup Tables in C++ format to VHDL.
    • v2sc is a Verilog to SystemC translator, for non-profit and educational uses only, not for moneymaking projects.
    • vaster is a Verilog RTL to SystemC Cycle-accurate model translator.
    • Another v2sc tool covnerts VHDL or Verilog to SystemC. This one is a GPL3 tool.
    • Verilog2C++ trnslates Verilog to C++ code.
    • Spark is a C to VHDL converter. It appears to be a dead project, and the download page doesn't give a link to the 1.3 version for Linux, though there is a 1.3 Linux binary in their downoad directory. They also have a book about High Level Synthesis.
    • vhd2vl is a free/open-source VHDL to Verilog translator.
    • Ocean Logic has a free VHDL to Verilog translator as well.
    • vhdlc is a VHDL to C++ translator
    • MyHDL allows you to write RTL in Python, and then convert to Verilog or VHDL for simulation and FPGA tools.
    • Chips is another Python based HDL, which can import and export VHDL.
    • Rapid HDL allows you to generate Verilog RTL in Visual Studio. I can't tell if you wrote RTL in C# and translate it, or if their generator is written in C#.
    • Confluence by Tom Hawkins is a retired project, apparently useful for converting design languages. Toward bottom of his web page. The original website from the Wayback Machine. Confluence now contains what was Informal, and this is your pathway to formal verification with NuSmv.
    • FNF is another netlist format/language translator, or it may simply point back to Confluence. Can't quite tell.
    • Lava is another Haskell based HDL, with design concepts that involve circuit placement as well as logic description. It can be downloaded here, setup instructions here, and a guide to using Lava is here. Here's some Lava2000 info.
    • ForSyDe is another Haskell HDL with compiler to VHDL.
    • Hydra is another Haskell HDL. Hyra's author says of Lava :
      Lava is essentially a clone of Hydra the way it was from around 1985 to about 1992.
    • BlueSpec is a commercial HDL based on Haskell/SystemVeriolog. (Not sure if it's now a combination, or if a new version replaces Haskell with SystemVerilog)
    • Atom-HDL supercedes Confluence and HDcaml. I'm unable to find a download for this, as funhdl.org seems to be overrun by spamming squatters, and the Wayback Machine doesn't seem to have the download file archived. :(
    • TRS was Tom's precursor to Atom-HDL.
    • CLasH is a Haskell to VHDL translator.
    • HDCaml is another retired project which superceded Confluence(?) and is an Open Caml based HDL. See bottom of linked page, and the original site in the Wayback Machine.
    • GEZEL is a cycle-accurate HDL with conversion to VHDL.
    • Cyclicity CDL is an HDL with a compiler to Verilog synthesizable RTL code. It can also compile to C for simulation, and comes with its own simulation engine.


  • HCT is an HDL model complexity reporting tool.
  • QFSM is a free/open source Finite State Machine Editor for Linux. It can output Verilog and VHDL code from the state machine diagram design, though I see it as more of a documentation tool than a code generating tool.
  • FSMDesigner is another free/open source Finite State Machine editor.
  • SMgen is a Finite State Machine generator using behavioral-Verilog-alike input files, synthesizing to RTL.
  • NuSMV seems to be part of formal model checking methodology. Can be used with Icarus Verilog via Confluence.
  • CBMC is a free/open source Bounded Model Checker with support for SystemC (using Scoot), and can compare C/C++ models to Verilog.
  • EBMC is a Bounded Model Checker for Verilog.
  • jtlv is a framework for formal verification algorithms.
  • equiitg is a formal verification between Verilog, Blif, Edif formats.
  • PSIM PowerPC Simulator, is a software simulator for the PowerPC instruction set. I suppose this needs moved to a more appropriate page here, but maybe it can be used with a design simulation as well, particularly if using Verilator?
  • ZamiaCad sounds like it's going to be a language-independent design environment.
  • SimIt is a cycle accurate model/simulator for ARM

Eclipse is a free/open source programming environment for Java, C/C++, etc. It has syntax coloring and error checking tools for a variety of languages, including Verilog and VHDL.
  • Simplifide is a VHDL/Verilog/SystemVerilog IDE plugin for Eclipse.
  • Excelsior is a VHDL/Verilog IDE plugin for Eclipse
  • veditor is a Verilog/VHDL IDE plugin for Eclipse.
  • sveditor is a Verilog/SystemVerilog IDE plugin for Eclipse.
  • Signs is a plugin for netlists, waveforms, etc. for VHDL and other HDLs.
  • eWave is a plugin to edit/view timing diagrams
  • TimeSquare is a plugin for viewing VCD wave files, among other things.
  • ivi has converted to a set of Eclipse Plugins for working with Icarus Verilog.
  • Design and Verification Tools is a commercial IDE plugin for E and SystemVerilog, and also does linting, interfacing with simulators, etc.
  • Sigasi is a commercial IDE plugin for VHDL
  • How to use Eclipse for SystemC in Ubuntu

Daedalus Design is a framework/design flow for SoC (multimedia/multiprocessor) to FPGA.

Wikipedia has a list/comparison of free EDA tools.
OpenCollector is a list of free and/or open-source EDA/CAD tools